Input (Gate-source loop):

                                                                         -V_GG – I_GR_G – V_GS = 0

              since I_G = 0 A                                                 V_GG = - V_GS

Ouput (Drain-source loop):

                                                                            V_DD – I_DR_D – V_DS = 0

                                                                                     R_D = V_DD - V_DS/ I_D

Shockley’s Equation:

                                                                               I_D = I_DSS ( 1 – V_GS/V_P ) ²

Parameters Used:

                                                    V_P = -3.5V                                    V_GG = -1V

                                                    V_DD = 25V                                      V_DS = 12.5V

                                                    I_DSS = 8 mA

..I_DSS is expressed in EWB as conductance coefficient (b):

                                                                              b =  I_DSS/|V_P|²

                                                                                                b =  8mA/|-3.5|²

                                                                                               b = 0.000653 , this is the value given in the FET characterisitics

Computing for I_D:

..in order to ensure that our FET is in proper operation, V_GG = -1V is chosen which is approximately one-thirds of the pinch-off voltage and an I_D which is half of the maximum drain current.

                                                                            I_D = I_DSS ( 1 – V_GS/V_P ) ²

           Since V_GG = 1V , V_GS = -1V                     I_D = 8mA [ 1 – (-1/-3.5) ] ²

                                                                            I_D = 4.082 mA

Computing for R_D:

Resistors are external components of the circuit, therefore assigning resistance values in design is greatly discouraged.

                                                                                    R_D = V_DD - V_DS/I_D

                                                                                  R_D =  25V – 12.5V/4.082mA

                                                                                    R_D = 3.07 kΩ  

   …standard coimmercial values can be used in actual design, but for the purpose of accuracy of results between the computed and simulated value, rounding off of values is avoided.                                                                                         

Simulated Output:

Computed Values:                       V_GS = -1V                                      V_DD = 25V                                     

                                                    V_DS = 12.5V                                      I_D = 4.082 mA

                                                     R_D = 3.07 kΩ  

 The simulated and computed values closely match. R_G does not need any strenous computation since it is only present to ensure that V_i ( ac voltage input) appears at the input io the FET ampflifier.

Input (Gate-source loop):

                                                                         – I_GR_G – V_GS -I_DR_S = 0

               since I_G = 0 A                                                 V_GS = -I_DR_S

Ouput (Drain-source loop):

                                                                            V_DD – I_DR_D – V_{DS  -} I_DR_S = 0

                                                                                  R_D = V_DD - V_{DS -} I_DR_{S /}I_D

Parameters Used:

                                                    V_P = -3.5V                                     V_GS = -1V

                                                    V_DD = 25V                                      V_DS = 12.5V

                                                    I_DSS = 8 mA

..I_DSS is expressed in EWB as conductance coefficient (b):

                                                                              b =  I_DSS/|V_P|²

                                                                                                  b =  8mA/|-3.5|²

                                                                                                  b = 0.000653 , this is the value given in the FET characterisitics

Computing for I_D:

..in order to ensure that our FET is in proper operation, V_GG = -1V is chosen which is approximately one-thirds of the pinch-off voltage and an I_D which is half of the maximum drain current.

                                                                            I_D = I_DSS ( 1 – V_GS/V_P ) ²

           Since V_GG = 1V , V_GS = -1V                     I_D = 8mA [ 1 – (-1/-3.5) ] ²

                                                                            I_D = 4.082 mA

Computing for R_S:

Resistors are external components of the circuit, therefore assigning resistance values in design is greatly discouraged.

                                                                                    V_GS = -I_DR_s

         R_D =  -I_S/ V_GS

     R_S =  -4.082 mA/-1 V

                                                                                    R_S = 245 Ω

   …standard coimmercial values can be used in actual design, but for the purpose of accuracy of results between the computed and simulated value, rounding off of values is avoided.                                                                                         

Computing for R_D:

      R_D = V_DD - V_{DS -} I_DR_{S /}I_D

                                                                     R_D = 25V – 12.5V _- (4.082mA)(245Ω) _/4.082mA

                                                                                  R_D = 2.8175 kΩ

Simulated Output:

Computed Values:                       V_GS = -1V                                          V_DD = 25V                                     

                                                    V_DS = 12.5V                                       I_D = 4.082 mA

                                                     R_D = 2.817 kΩ                                  R_S = 245 Ω                                            

 The simulated and computed values closely match. R_G does not need any strenous computation since it is only present to ensure that V_i ( ac voltage input) appears at the input io the FET ampflifier.

Input (Gate-source loop):

                                                                              V_G – V_GS - I_DR_S = 0                  , wherein V_G = V_DDR₂/R₁+R₂

                                                             V_GS = V_G - I_DR_S                                 

      … the input loop is a linear equation, therefore its relationship is proportional.

   At VGS = 0                                         V_GS = V_G - I_DR_S     

                  0 = V_G - I_DR_S   

                   V_G = I_DR_S                    

Ouput (Drain-source loop):

                                                                            V_DD – I_DR_D – V_{DS  -} I_DR_S = 0

                                                                                  R_D = V_DD - V_{DS -} I_DR_{S /} I_D

Shockley’s Equation:

                                                                               I_D = I_DSS ( 1 – V_GS/V_P ) ²

..I_DSS is expressed in EWB as conductance coefficient (b):

                                                                              b =  I_DSS/|V_P|²

                                                                                                 b =  8mA/|-3.5|²

                                                                                                b = 0.000653 , this is the value given in the FET characterisitics

Computing for I_D:

..in order to ensure that our FET is in proper operation, VGS = -1 is intended which is approximately one-thirds of the pinch-off voltage and an I_D which is half of the maximum drain current.

                                                                            I_D = I_DSS ( 1 – V_GS/V_P ) ²

           Since V_GG = 1V , V_GS = -1V                     I_D = 8mA [ 1 – (-1/-3.5) ] ²

                                                                            I_D = 4.082 mA

Computing for R_S:

Resistors are external components of the circuit, therefore assigning resistance values in design is greatly discouraged. In order to solve for Rs, we must first assume a value of V_G..

Let V_G = 1 V,

     V_GS = V_G - I_DR_S     

         R_S =  V_G - V_GS/  I_D

     R_S =    1V – (-1V)/  4.082mA

                                                                                    R_S = 490 Ω

   …standard coimmercial values can be used in actual design, but for the purpose of accuracy of results between the computed and simulated value, rounding off of values is avoided.                                                                                         

Computing for R_D:

      R_D = V_DD - V_{DS -} I_DR_S/  I_D

                                                                     R_D = 25V – 12.5V _- (4.082mA)(490Ω) _/4.082mA

                                                                                  R_D = 2.573 kΩ

Computing for R1:

                                                                                      V_G = V_DDR₂/R₁+R₂

                                                                                      V_GR₁ + V_GR₂ = V_DDR₂

                                                                                      R₁   =   V_DDR₂ - V_GR_2/V_G

                                                                                      R₁   =     R₂(V_DD - V_G)/V_G

..since R2 is usually less than R1, it is ideal to assume a value for R2

                                                                                      R₁   =     100 kΩ(25V – 1V)/1V

                                                                                      R₁   =    2.4 MΩ

Simulated Output:

Computed Values:                       V_GS = -1V                                          V_DD = 25V                                     

                                                    V_DS = 12.5V                                       I_D = 4.082 mA

                                                     R_D = 2.573 kΩ                                  R_S = 490Ω      

                                                      V_G = 1V              R1 = 100 kΩ          R2 = 2.4 MΩ

 The simulated and computed values closely match.

Voltage feedback bias is not applicable for JFET’s because it only conducts a negative gate voltage while this biasing usually employs the use of  positive voltage which is feedback from the voltage source. Depletion MOSFET which can still use the Shockley’s equation can be used for voltage feedback biasing since this device can conduct beyond its maximum drain current ratings. Also it can conduct a positive voltage as its gate potential. But ideally,  voltage feedback can be of best used for enhancement-type MOSFET, but its calculation is much a different approach compared to D-MOSFET since Shockley’s equation is not applicable for this device.

Since I_G = 0 mA, V_GS = V_DS.

                                                                         -V_GG – I_GR_G – V_GS = 0

                                                                             V_GG = - V_GS

Ouput (Drain-source loop):

                                                                            V_DD – I_DR_D – V_DS = 0

                                                                                     R_D = V_DD - V_DS/I_D

Shockley’s Equation:

                                                                               I_D = I_DSS ( 1 – V_GS/V_P ) ²

Conductance coefficient (b):

 ..the conductance coefficeent of Depletion-MOSET is different from JFET..here is its equation:

                                                                              b =   2I_DSS/|V_P|²

                                                                                                   b =  2*4mA/|-3.5|²

                                                                                                  b = 0.00065306

Computing for I_D:

                                                         .. V_GS = V_DS, since V_DS = V_DD/2…V_DS = 12.5V.

                                                                            I_D = I_DSS ( 1 – V_GS/V_P ) ²

                                                                I_D = 8mA [ 1 – (12.5/-3.5) ] ²

                                                                            I_D = 83.59 mA

Computing for RD:

                                                                                     R_D =  25V- 12.5V/83.59 mA

                                                                                     R_D = 149.54 Ω

   …standard coimmercial values can be used in actual design, but for the purpose of accuracy of results between the computed and simulated value, rounding off of values is avoided.   

Simulated Output:

Computed Values:                       V_GS = 12.5 V                                          V_DD = 25V                                     

                                                    V_DS = 12.5V                                       I_D = 83.59 mA

                                                     R_D = 149.54 Ω                                 

 The simulated and computed values closely match. R_G does not need any strenous computation since it is only present to ensure that V_i ( ac voltage input) appears at the input io the FET ampflifier.

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